The present invention relates to methods and apparatus for controlling static random access memory (SRAM), and in particular for reducing the power dissipation of the SRAM based on the data stored therein.
SRAM memory cells store data in the form of complementary low voltage and high voltage at opposite sides of the cell. An SRAM, unlike dynamic random access memory (DRAM), maintains the data content of the memory calls as long as power is applied to the cell. DRAM memory cells, on the other hand, are periodically refreshed with the stored data content. An SRAM cell includes a “true” node associated with a bit line of the SRAM memory and a complementary node associated with a complementary bit line of the SRAM memory. When the true node is read as a high voltage, the value of the SRAM memory cell is digital one. If the true node is read as a low voltage, the value of the SRAM memory cell is a digital zero.
During write and read cycles, a conventional SRAM memory system will employ a pre-charge circuit to drive the bit line and the complementary bit line to a power supply voltage of the SRAM memory, Vdd, before data is written to the memory cell. During the time that the data is actually written to the SRAM memory cell, a write buffer drives the bit line and the complementary bit line. During the read operation, the active components of the SRAM memory cell itself will drive the bit line, which is sensed to determine the value of the stored data bit in the cell. The amount of power consumed and dissipated by an SRAM memory cell during a read operation depends on the value of the data stored in the cell. In general, when the stored data bit is such that the true node is low (which is usually associated with a stored data bit at logic level 0) the cell consumes and dissipates more power than when the stored data bit is such that the true node is high (which is usually associated with a stored data bit at logic level 1).
Successive read cycles of a plurality of SRAM memory cells (in which the stored data are at a logic level 1) at a relatively high frequency clock will produce significant power dissipation in the SRAM memory. The power dissipation problem becomes significantly worse as the frequency of the clock increases and the size of the SRAM increases, which is an ongoing circumstance as higher and higher memory performance remains a design goal.
Accordingly, there is a need in the art for a new approach to controlling SRAM memory cells in order to counteract the increase in power dissipation resulting from higher and higher clock frequencies and larger and larger SRAM memories.